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Ordering number : ENA0460A
LC723661, LC723662, LC723663
Overview
CMOS IC
Electronic tuning radio for car audio
ETR Controllers
The LC723661, 723662 and 723663 are ETR controllers that can support up to 64KB of ROM and up to 4KB of RAM. These are an 80-pin version of the 100-pin LC723780 series. They have a built-in serial I/O port and 6-input 8-bit A/D converter to enhance communication with the internal and external devices.
Functions
* ROM * RAM : Up to 32K steps (32767x16-bits) The subroutine area holds 4K steps (4,096x16-bits) : Up to 8Kx4-bits (In banks 00 through 7F) LC723661-ROM 32KB, RAM 2KB LC723662-ROM 48KB, RAM 2KB LC723663-ROM 64KB, RAM 4KB : 32 levels : Two channels. These circuits can support both 2-wire and 3-wire 8-bit communication techniques, and can be switched between MSB first and LSB first operation. One of six internally generated serial transfer clock rates can be selected: 12.5kHz, 37.5kHz, 187.5kHz, 281.25kHz, 375kHz, and 450kHz : Five interrupt inputs (pins INT0, 1, 4, and 5, and the HOLD pin) These interrupts can be set to switch between rising and falling edges, although the HOLD pin only supports falling edge detection. : Six interrupts ; four internal timer interrupts, and two serial I/O interrupts.
* Stack * Serial I/O
* External interrupts * Internal interrupts
* This production is produced and sold by SANYO under license of the Silicon Storage Technology Inc. Specifications and information herein are subject to change without notice.
Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before usingany SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein.
92006HKIM B8-9066,9070,9071 No.0460-1/12
LC723661, 723662, 723663
: 11 levels Interrupts are prioritized in hardware as follows : HOLD pin>INT0 pin>INT1 pin> INT4 pin>INT5 pin> S-I/O0>S-I/O1>Internal TMR0>Internal TMR1>Internal TMR2> Internal TMR3 * A/D Converter : 8-bit resolution and 6 inputs * General-purpose ports : Input ports : 10 Output ports : 2 I/O ports : 48 (These pins can be switched between input and output in 1-bit units.) * PLL block : Includes a sub-charge pump for high-speed locking. Supports dead zone control. Built-in unlock detection circuit Twelve reference frequencies : 1kHz, 3kHz, 3.125kHz, 5kHz, 6.25kHz, 9kHz, 10kHz, 12.5kHz, 25kHz, 30kHz, 50kHz, and 100kHz * Universal counter : This 20-bit counter can be used for either frequency or period measurement and supports four measurement (calculation) periods : 1ms, 4ms, 8ms, and 32ms * Timers : Two fixed timers and two programmable timers (8-bit counters) TMR0 : Supports four periods : 10s, 100s, 1ms, and 5ms TMR1 : Supports four periods : 10s, 100s, 1ms, and 10ms TMR2 and TMR3 : Programmable 8-bit counters. Input clocks with 10s, 100s, and 1ms One 125-ms timer flip-flop provided * Beep circuit : Provides 12 fixed beep tones : 500Hz, 1kHz, 2kHz, 2.08kHz, 2.2kHz, 2.5kHz, 3.33kHz, 3.75kHz, 4.17kHz, and 7.03kHz Programmable 8-bit beep tone generator. Reference clocks with frequencies of 50kHz, 15kHz, and 5kHz. * Reset : Built-in voltage detection reset circuit External reset pin * Cycle time : 1.33s/833ns (All instructions are one word), X'tal : 4.5MHz/7.2MHz (4.5MHz when initialization is to be performed. When 7.2MHz is used, select 4.5MHz by software.) * Halt mode : Stops the operation clock of the controller. There are four conditions that can clear Halt mode : Interrupt requests, timer flip-flop overflows, port PA inputs, and HOLD pin inputs. * Operating supply voltage : 4.5 to 5.5V (Microcontroller block only : 3.5 to 5.5V) * Package : QIP80E * OTP version : LC72F3661 * Development tools : Emulator : RE128V Evaluation chip : LC72EV3780 Evaluation board : EB-72EV3780 * Interrupt nesting levels
No.0460-2/12
LC723661, 723662, 723663
Specifications
Absolute Maximum Ratings at Ta = 25C VSS = 0V
Parameter Maximum supply voltage Input voltage Output voltage Symbol VDD max VIN1 VOUT1 VOUT2 Output current IOUT1 IOUT2 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg All input pins PJ-PORT All input pins other than VOUT1 PJ-PORT PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PQ, PR, PS-PORT, EO1, EO2 Ta = -40 to +85 C Conditions Ratings -0.3 to +6.5 -0.3 to VDD+0.3 -0.3 to +14 -0.3 to VDD+0.3 0 to 5 0 to 3 400 -40 to +85 -45 to +125 Unit V V V V mA mA mW C C
Allowable Operating Range at Ta = -40 to +85C, VDD = 3.5 to 5.5V
Parameter Supply voltage Symbol VDD1 VDD2 VDD3 Input high-level voltage VIH2 VIH3 VIH4 Input low-level voltage VIL1 VIL2 VIL3 VIL4 Input amplitude VIN1 VIN2 VIN3 Input voltage range Input frequency VIN6 FIN1 FIN2 FIN3 FIN4 FIN5 FIN6 FIN7 FIN8 VIH1 PLL operation Memory retention CPU operation PB, PH, PI, PL, PM, PN, PO, PQ, PR, PS-PORT, HCTR, LCTR PD, PE, PF, PG, PK-PORT, LCTR (in period measurement mode), HOLD, RESET SNS PA-PORT PB, PH, PI, PL, PM, PN, PO, PQ, PR, PS-PORT, HCTR, LCTR PA, PD, PE, PF, PG, PK-PORT, LCTR (in period measurement mode), RESET SNS HOLD XIN FMIN FMIN, AMIN, HCTR, LCTR ADI0 to ADI7 XIN FMIN: VIN2, VDD1 FMIN: VIN3, VDD1 AMIN(H) : VIN3, VDD1 AMIN(L) : VIN3, VDD1 HCTR: VIN3, VDD1 LCTR: VIN3, VDD1 LCTR (in period measurement) : VIH2, VIL2, VDD1 Pins Ratings min 4.5 1.1 3.5 0.7VDD 0.8VDD 2.5 0.6VDD 0 0 0 0 0.5 0.07 0.04 0 4.0 10 10 2.0 0.5 0.4 100 1 4.5 typ 5.0 mx 5.5 5.5 5.5 VDD VDD VDD VDD 0.3VDD 0.2VDD 1.1 0.4VDD 1.5 1.5 1.5 VDD 8.0 150 130 40 10 12 500 20x103 V V V V V V V V Vrms Vrms Vrms V MHz MHz MHz MHz MHz MHz kHz Hz V uit
No.0460-3/12
LC723661, 723662, 723663
Electrical Characteristics in the allowable operating ranges
Parameter Input high-level current Symbol IIH1 IIH2 IIH3 XIN : VI = VDD = 5.0V FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0V PA, PB, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO, PQ, PR, PS-PORT, SNS, HOLD, RESET, HCTR, LCTR: VI = VDD = 5.0V (with the ports PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PQ, PR, and PS-PORT set to input mode) Input low-level current IIL1 IIL2 IIL3 XIN : VI = VDD = VSS FMIN, AMIN, HCTR, LCTR: VI = VDD = VSS PA, PB, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO, PQ, PR, PS-PORT, SNS, HOLD, RESET, HCTR, LCTR: VI = VSS (with the ports PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PQ, PR, and PS-PORT set to input mode) Hysteresis Output high-level voltage VH VOH1 VOH2 VOH3 Output low-level voltage VOL1 VOL2 VOL3 VOL4 Output off leakage current IOFF2 IOFF3 A/D conversion error Rejected pulse width Power down detection voltage Power supply current IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 VDD1 : FIN2 = 130MHz Ta = 25C VDD1 : FIN2 = 130MHz Ta = 25C VDD2 : Halt mode Ta = 25C, X'tal : 4.5 MHz VDD2 : Halt mode Ta = 25C, X'tal : 7.2MHz Backup mode (OSC stopped) VDD = 5.5V, Ta = 25C Backup mode (OSC stopped) VDD = 2.5V, Ta = 25C *2 (Fig. 2) *2 (Fig. 2) *1 (Fig. 1) PREJ1 VDET IOFF1 PD, PE, PF, PG, PK-PORT, RESET, LCTR (in period measurement) PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PQ, PR, PS-PORT: IO = -1mA EO1, EO2: IO = -500A XOUT: IO = -200A PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PQ, PR, PS-PORT: IO = -1mA EO1, EO2: IO = -500A XOUT : IO = -200A PJ-PORT : IO = -5mA PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PQ, PR, PS-PORT EO1, EO2 PJ-PORT ADI0 to ADI7 SNS 2.7 3.0 5 5.5 0.45 0.55 5 1 -3 -100 -5 -1.5 0.1VDD VDD-1.0 VDD-1.0 VDD-1.0 1.0 1.0 1.5 2.0 +3 +100 +5 +1.5 50 3.3 10 11 0.2VDD V V V V V V V V A nA A LSB s V mA mA mA mA A A 3 A 2.0 4.0 5.0 10 15 30 A A 3 A Pins Ratings min 2.0 4.0 typ 5.0 10 max 15 30 unit A A
*1: Twenty instruction steps are executed every millisecond. The PLL, universal counter, and other functions are stopped.
No.0460-4/12
LC723661, 723662, 723663
Test Circuits
20pF A
4.5MHz
20pF
XOUT VDD RES XIN LCTR VSS FMIN AMIN HCTR TEST 1, 2
SNS
HOLD PA, PH, PI
Ports PB through PG, and PJ through PS are all left open. However, ports PB through PG, PK through PS are left open in output mode.
ILC05608
Figure 1. HALT current test condition
20pF A
20pF
4.5MHz
XOUT VDD RES XIN LCTR VSS FMIN AMIN HCTR TEST 1, 2
SNS
HOLD
Ports PA through PS are all left open.
ILC05609
Figure 2. BACK UP current test condition
Package Dimensions
unit:mm (typ) 3174A
23.2 20.0 64 65 41 40
80 1 0.8 (0.8)
3.0max
25 24 0.35 0.15
0.1
(2.7)
SANYO : QIP80E(14X20)
14.0
17.2
0.8
No.0460-5/12
LC723661, 723662, 723663
Pin Assignment
PH0/ADI0 PH1/ADI1 66 VSSADC 65 VDDPLL VSSPLL
80
79
78
77
76
75
74
73
72
71
70
69
68
RESET
TEST1
XOUT
HOLD
HCTR
LCTR
AMIN
FMIN
SNS
EO1
EO2
67
XIN TEST2 VREG VSSCPU SI0/PG3 SO0/PG2 SCK0/PG1 PG0 SI1/PF3 SO1/PF2 SCK1/PF1 PF0 PE1 PE0 PD3 PD2 PD1/INT5 PD0/INT4 PB3 PB2 PB1 PB0 PA3 PA2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 I I/O I/O I/O I/O I/O
I
64 63 I 62 61 60 59 I/O 58 57 56 I/O 55 54 53 52
PI0/ADI4 PI1/ADI5 PI2/ADI6 PI3/ADI7 PJ0 PJ1 PK0/INT0 PK1/INT1 PL0 PL1 PL2 PL3 PM0 PM1 PM2 PM3 PN0/BEEP PN1 PN2 PN3 PO0 PO1 PO2 PO3
O
I/O
I/O I/O 51 50 49 48 47 46 45 44 I/O 43 42 41 38 39 PQ1 40 PQ0 Top view No.0460-6/12
I/O
I/O
VDDPORT
VSSPORT
PQ3
PQ2
PA1
PA0
PS3
PS2
PS1
PS0
PR3
PR2
PR1
PR0
LC723661, 723662, 723663
Block Diagram
XIN XOUT FMIN DIVIDER SYSTEM CLOCK GENERATOR 1/ 16, 1/ 17 PROGRAMMBLE DIVIDER REFERENCE DIVIDER SELECTOR PHASE DETECTOR UNLOCK F/F EO1 EO2
AMIN SNS SNS VDD VSS HCTR 1/2 LCTR UNIVERSAL COUNTER (20bits) V-DET TIMER PROGx2 FIXx2 DATA LATCH BUS DRIVE. RESET HOLD TEST1 TEST2 PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 DTR / ADR RAM 4Kx4bit 8Kx4bit ADDRESS DECODER BANK DATA LATCH BUS DRIVE. DATA LATCH BUS DRIVE. BUS CONTROL ROM 16Kx16bit 24Kx16bit 32Kx16bit INSTRUCTION DECODER ADDRESS DECODER DATA LATCH BUS DRIVE. SKIP DATA LATCH BUS DRIVE. PF STACK 32x24bits (PC, BANK, CF, PF) MPX PO3 PO2 PO1 PO0 PN3 PN2 PN1 PN0 / BEEP PS3 PS2 PS1 PS0 PR3 PR2 PR1 PR0 PQ3 PQ2 PQ1 PQ0 SNSF / F PLL DATA LATCH
BUS DRIVE. DATA LATCH BUS DRIVE.
INT4 / PD0 INT5 / PD1 PD2 PD3 PE0 PE1
DATA LATCH BUS DRIVE. INTERRUPT DATA LATCH BUS DRIVE. PROGRAM COUNTER
PF0 SCK1 / PF1 SO1 / PF2 SI1 / PF3
DATA LATCH BUS DRIVE. SIO x2
BEEP GEN (PRG / FIX)
LATCH A ALU LATCH B
JUDGE
DATA LATCH BUS DRIVE. DATA LATCH
PM3 PM2 PM1 PM0 PL3 PL2 PL1 PL0 PK1 / INT1 PK0 / INT0
PG0 SCK0 / PG1 SO0 / PG2 SI0 / PG3 ADI0 / PH0 ADI1 / PH1
DATA LATCH BUS DRIVE. BUS DRIVE.
STATUS READ REGISTER
BUS DRIVE. DATA LATCH BUS DRIVE.
MPX(8ch) ADI4 / PI0 ADI5 / PI1 ADI6 / PI2 ADI7 / PI3 BUS DRIVE.
A / D-C (8bits)
INTERRUPT CONTROL
STATUS WRITE REGISTER
INTERRUPT DATA LATCH PJ1 PJ0
BUS
ILC05610
No.0460-7/12
LC723661, 723662, 723663
Pin Description
Pin name PA0 PA1 PA2 PA3 Pin No. 26 25 24 23 I/O I Dedicated input ports. These ports are designed with a low threshold voltage. Input is disabled in Backup mode. Pin explanation Equivalent circuit
BACK UP
ILC05529
PB0 PB1 PB2 PB3
22 21 20 19
I/O
General-purpose I/O ports. The mode (input or output) is set using the IOS2 instruction. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset.
BACK UP
ILC05530
PD0/INT4 PD1/INT5 PD2 PD3
18 17 16 15
I/O
General-purpose I/O and external interrupt shared function ports. The input formats are Schmitt inputs. The external interrupt function is enabled when the external interrupt enable flag is set. * When used as general-purpose I/O ports : The mode (input or output) is set in 1-bit units using the IOS2 instruction. * When used as external interrupt pins : The external interrupt functions are enabled by setting the corresponding external interrupt enable flag (INT4EN or INT5EN). In this case, the pins must be set to input mode in advance. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset.
PE0 PE1
14 13
I/O
General-purpose I/O ports The input formats are Schmitt inputs. The mode (input or output) is set in 1-bit units using the IOS1 instruction Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset.
ILC05532
BACK UP
PF0 PF1/SCK1 PF2/SO1 PF3/SI1 PG0 PG1/SCK0 PG2/SO0 PG3/SI0
12 11 10 9 8 7 6 5
I/O
General-purpose I/O ports with shared functions as serial I/O ports. The input formats are Schmitt inputs. The IOS1 instruction is used to switch between the general-purpose I/O port and serial I/O port functions. * When used as general-purpose I/O ports : The pins are set to the general-purpose I/O port function using the IOS1 instruction. The mode (input or output) is set in 1-bit units using the IOS1 instruction * When used serial I/O ports : The pins are set to the serial I/O port function using the IOS1 instruction. [Pin states when set to the serial I/O port function] PF0, PG0 ... General-purpose I/O PF1, PG1 ... SCK input or output PF2, PG2 ... SO output PF3, PG3 ... SI input Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset.
Continued on next page.
No.0460-8/12
LC723661, 723662, 723663
Continued from preceding page.
Pin name XIN XOUT Pin No. 1 80 I/O I O
XIN XOUT
ILC05534
Pin explanation Connections for 4.5MHz/7.2MHz crystal oscillator element
Equivalent circuit
EO1 EO2
78 77
O
Main charge pump outputs. These pins output a high level when the frequency of the local oscillator divided by n is higher than that of the reference frequency, and they output a low level when that frequency is lower. They go to the high-impedance state when the frequencies match. These pins go to the high-impedance state in Backup mode, after a power on reset, and in the PLL stopped state.
ILC05535
VDDPORT VDDPLL
31 73
-
+ pin of power supply (These pins must connected to VDD.) The VDDPORT pin is mainly supply power for the peripheral I/O blocks. The VDDPLL pin is mainly for the PLL circuits and the regulator.
VSSCPU VSSPORT VSSADC VSSPLL
4 32 65 76
Power supply ground pin (These pins must be connected to ground.) The VSSPORT pin is mainly supply power for the peripheral I/O blocks. The VSSPLL pin is mainly for the PLL circuits and the regulator. The VSSCPU pin is mainly used by the CPU block. The VSSADC pin is mainly used by the ADC block.
VREG FMIN
3 75
O I
Internal low voltage output. Connect a bypass capacitor to this pin. FM VCO (local oscillator) input. This pin is selected with CW1 in the PLL instruction. The signal input to this pin must be capacitor coupled. Input is disabled in Backup mode, after a power on reset, and in the PLL stopped state.
AMIN
74
I
AM VCO (local oscillator) input. This pin is selected and the band set with CW1 (b1, b0) in the PLL instruction. b1 1 1 b0 0 1 Band 2 to 40MHz (SW, AM upconversion) 0.5 to 10MHz (MW, LW)
The signal input to this pin must be capacitor coupled. Input is disabled in Backup mode, after a power on reset, and in the PLL stopped state. HCTR 72 I Universal counter and general-purpose input shared function input port. The IOS1 instruction is used for switching between the universal counter and general-purpose input functions. * When used for frequency measurement : The universal counter function is set up with the IOS1 instruction. The counter is controlled using UCS and UCC instructions. Since this pin functions as an AC amplifier in this mode, the input signal must be input with capacitor coupling. * When used as a general-purpose input pin : The general-purpose input function is set up with the IOS1 instruction. Data is read from the port using the INR (b0) instruction. Input is disabled in Backup mode. (The input pin will be pulled down.) The universal counter function is selected after a power on reset.
ILC05536
PLL Stop instruction
Continued on next page.
No.0460-9/12
LC723661, 723662, 723663
Continued from preceding page.
Pin name LCTR Pin No. 71 I/O I Pin explanation Universal counter (frequency or period measurement) and generalpurpose input shared function input port. The IOS1 instruction is used for switching between the universal counter and general-purpose input functions. * When used for frequency measurement : The universal counter function is set up with the IOS1 instruction. Set up LCTR frequency measurement mode with the UCS instruction, and control operation with the UCC instruction. Since this pin functions as an AC amplifier in this mode, the input signal must be input with capacitor coupling. * When used for period measurement : The universal counter function is set up with the IOS1 instruction. Set up LCTR frequency measurement mode with the UCS instruction, and control operation with the UCC instruction. Since the bias feedback resistor is disconnected in this mode, the input signal must be input with DC coupling. * When used as a general-purpose input pin : The general-purpose input port function is set up with the IOS1 instruction. Data is read from the port using the INR (b1) instruction. Input is disabled in Backup mode. (The input pin will be pulled down.) The universal counter function (HCTR frequency measurement mode) is selected after a power on reset. SNS 70 I Voltage sense and general-purpose input shared function port. This input circuit is designed with a low input threshold voltage. * When used as a voltage sense input : The pin is used to test for power failures on the return from Backup mode. Application can test this condition using the internal SNS flip-flop. The SNS flip-flop can be tested with the TST instruction. (This usage requires external components, capacitors and resistors. For the sample application circuit, see the user's manual.) * When used as a general-purpose input port : When used as a general-purpose input port the pin state can be tested with the TST instruction. Unlike the other input ports, input to this pin is not disabled in Backup mode and after a power on reset. As a result, through currents must be taken into account when designing applications that use this pin as a general-purpose input. HOLD 69 I Power supply monitor (with interrupt function) This is designed with a high input threshold voltage. This pin is normally connected to the ACC line and used for power off detection. When a power off state is detected, the HOLDON flag and the hold interrupt request flag will be set. To enter Backup mode, execute a CKSTP instruction when the HOLD pin is low. Set this pin high to clear Backup mode. RESET 68 I System reset pin. When the CPU is operating or in Halt mode, the system is reset when this pin is held low for at least one machine cycle. Execution starts with the PC pointing to location 0. At this time the SNS flip-flop is set. A low level must be applied for at least 50ms when power is first applied.
ILC05540
ILC05539
Equivalent circuit
PLL Stop instruction
ILC05536
ILC05539
Continued on next page.
No.0460-10/12
LC723661, 723662, 723663
Continued from preceding page.
Pin name PH0/ADI0 PH1/ADI1 PI0/ADI4 PI1/ADI5 PI2/ADI6 PI3/ADI7 Pin No. 67 66 64 63 62 61 I/O I Pin explanation General-purpose input and A/D converter input shared function ports. The IOS1 instruction is used to switch between the general-purpose input and the A/D converter input functions. * When used as general-purpose input ports : The general-purpose input port function is set up with the IOS1 instruction. (In bit units) * When used as A/D converter input pins : The A/D converter input port function is set up with the IOS1 instruction. (In bit units) The pin whose voltage is to be converted is specified with the IOS1 instruction, and the conversion is started with UCC instruction. Note : Since input is disabled for ports specified for the ADI function, executing an input instruction for such a port will always return a low level. Input is disabled in Backup mode. These ports are set up as general-purpose input ports after a power on reset. PJ0 PJ1 60 59 O General-purpose output ports (high-voltage output) Since these are open-drain output circuits, external pull-up resistors are required. The internal transistors are turned off (resulting in a high-level output) in Backup mode and after a power on reset. PK0/INT0 PK1/INT1 58 57 I/O General-purpose I/O and external interrupt shared function ports. The input formats are Schmitt inputs. The external interrupt function is enabled when the external interrupt enable flag is set. * When used as general-purpose I/O ports : The mode (input or output) is set in 1-bit units using the IOS1 instruction. * When used as external interrupt pins : The external interrupt functions are enabled by setting the corresponding external interrupt enable flag (INT0EN through INT3EN). Here, the pins must be set to input mode in advance. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset. PL0 to 3 PM0 to 3 56 to 53 52 to 49 I/O General-purpose I/O ports The mode is switched between input and output with the IOS instruction. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset. PN0/BEEP PN1 PN2 PN3 48 47 46 45 I/O General-purpose I/O port and beep tone output shared function ports. The IOS2 instruction is used to switch between the general-purpose I/O port and the beep tone output functions. * When used as general-purpose I/O ports: The general-purpose I/O port function is set up with the IOS2 instruction. (Pins PN1 through PN3 are dedicated general-purpose output pins.) * When used as the beep tone output pin: The beep tone output function is set up with the IOS2 instruction. The frequency is set up with the BEEP instruction. When this pin is used as the beep tone output pin, executing an output instruction for this pin only sets the internal latch and has no influence on the output. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset.
ILC05544
Equivalent circuit
BACK UP
To the A/D converter input
ILC05541
BACK UP
ILC05542
BACK UP
ILC05543
BACK UP
Continued on next page.
No.0460-11/12
LC723661, 723662, 723663
Continued from preceding page.
Pin name P00 P01 P02 P03 Pin No. 44 43 42 41 I/O I/O General-purpose I/O ports The mode is switched between input and output with the IOS instruction. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset. PQ0 to 3 PR0 to 3 PS0 to 3 40 to 37 36 to 33 30 to 27 I/O General-purpose I/O ports. The mode is switched between input and output with the IOS instruction, and data is input with the INR instruction and output with the OUTR instruction. The SPB, RPB, TPT, and TPF instruction cannot be used with these ports. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset. TEST1 TEST2 79 2 LSI test pins. These pins must be connected to GND.
ILC05544
Pin explanation
Equivalent circuit
BACK UP
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of September, 2006. Specifications and information herein are subject to change without notice.
PS No.0460-12/12

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